The present disclosure relates to semiconductor devices used as a switching element for a power supply circuit etc., and more particularly, to techniques which are effective in improving the efficiency of power conversion.
There has been a demand for an energy-saving power supply circuit. To meet the demand, it is required to reduce power loss to improve the efficiency of power conversion in a power conversion device, such as a DC-DC converter, an inverter, etc. In these devices, most of power loss occurs in a switching device, such as an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). Therefore, a reduction in power loss in the switching device would significantly contribute to an improvement in power conversion efficiency.
Power loss which occurs in a switching device includes conduction loss caused by passage of a current and switching loss caused by switching operation. Conduction loss can be reduced by decreasing the on-state resistance of the power semiconductor element, and switching loss can be reduced by increasing the switching speed of the power semiconductor element. Therefore, techniques have been developed for decreasing the on-state resistance of the power semiconductor element and increasing the switching speed of the power semiconductor element.
On the other hand, the power semiconductor element which operates at an increasingly higher frequency has been developed in order to reduce the size of a power supply circuit. For a DC-DC converter for use in a power supply circuit for a personal computer, a stationary game machine, etc., there has been a trend toward increasing the current in order to drive the central processing unit at high speed.
A DC-DC converter includes a high-side switch and a low-side switch. Each switch includes a power semiconductor element. Power conversion is performed by alternately switching the high-side switch and the low-side switch on/off in synchronization with each other. The high-side switch serves as a control switch for the DC-DC converter, and the low-side switch serves as a switch for synchronous rectification.
For example, when the high-side switch and the low-side switch are provided in a single package, parasitic inductance occurs due to wire bonding or printed circuit board traces of the package. In particular, when a main current flows through the parasitic inductance at the source terminal of the high-side switch, great induced electromotive force is generated. Therefore, turn-on of the high-side switch is delayed, leading to a deterioration in power conversion efficiency. Therefore, as a technique of improving the power conversion efficiency of the DC-DC converter, it has been proposed that the influence of parasitic inductance which is caused due to wire bonding or packaging is reduced by separating a gate drive path from a main current path (see Japanese Unexamined Patent Publication No. 2004-342735).
However, the DC-DC converter as described above has the following problems. Specifically, the increase in frequency and current of the DC-DC converter causes a delay in turn-on switching due to induced electromotive force generated by the parasitic inductance of lead traces in a chip which connect between a source electrode and a source terminal or between a drain electrode and a drain terminal, which is not required to be taken into account in the conventional art.
FIG. 14 is a circuit diagram showing a configuration of a switching device 300A which is a conventional semiconductor device. The switching device 300A of FIG. 14 includes a power semiconductor chip 301A, a drive circuit 302 which drives the power semiconductor chip 301A, a control signal source 303, an input power supply 304, a logic power supply 305, and a load resistor 306. The power semiconductor chip 301A has a transistor having a gate electrode G, a drain electrode D, and a source electrode S, a gate terminal 200, a drain terminal 201, and a source terminal 202. In the power semiconductor chip 301A, there are gate parasitic inductance (Lg) 307A, drain parasitic inductance (Ld) 307B, and source parasitic inductance (Ls) 307C which are caused by the internal trace structure. A main current 204 flows between the drain terminal 201 and the source terminal 202.
FIG. 15 is an enlarged plan view showing an electrode layout of the power semiconductor chip 301A of FIG. 14. A semiconductor multilayer arrangement 101 is formed on a substrate 100, and drain electrodes 103 and source electrodes 104 are formed on the semiconductor multilayer arrangement 101 with a space between each electrode. Gate electrodes 102 are formed between the drain electrodes 103 and the source electrodes 104. Thus, the power semiconductor chip 301A has a horizontal device structure. The drain electrodes 103 are connected to a drain lead trace 105 through vias 11D. Similarly, the source electrodes 104 are connected to a source lead trace 106 through vias 11S. The drain lead trace 105 is connected to the drain terminal 201, and the source lead trace 106 is connected to the source terminal 202.
FIG. 16 is a plan view showing a layout of the power semiconductor chip 301A of FIG. 14 on a printed circuit board (not shown). The output of the drive circuit 302 is connected to the gate terminal 200 of the power semiconductor chip 301A through a printed circuit board trace 4G. The drain terminal 201 of the power semiconductor chip 301A is connected to a drain region 205 of the printed circuit board through a printed circuit board trace 4D. The source terminal 202 of the power semiconductor chip 301A is connected to a source region 206 of the printed circuit board through a printed circuit board trace 4S. A ground terminal of the drive circuit 302 is connected to the source terminal 202 of the power semiconductor chip 301A through a printed circuit board trace 4GR. The main current 204 flowing through the printed circuit board flows from the drain region 205 of the printed circuit board to the source region 206 of the printed circuit board through the drain and source terminals 201 and 202 of the power semiconductor chip 301A.
The drive circuit 302 is grounded at the source. Note that, for example, an interlayer insulating film (not shown) is provided so that the printed circuit board trace 4GR connecting the ground terminal of the drive circuit 302 and the source terminal 202 together is not in contact with the gate terminal 200 or the drain terminal 201.
FIG. 17 is a waveform diagram showing that a gate-source voltage Vgs and a source voltage Vs in the power semiconductor chip 301A of FIG. 14 are easily affected by the source parasitic inductance 307C. As shown in FIG. 17, particularly when the source parasitic inductance 307C increases, the source voltage Vs increases due to induced electromotive force generated by flow of the main current 204, so that the rise and fall of the gate-source voltage Vgs are delayed. As a result, turn-on loss and turn-off loss increase, leading to a significant deterioration in power conversion efficiency.